View APW7093NI-TRL_639484.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APW7093
3A, 1MHz, Step Down DC/DC Regulator
Features
* * * *
Source/Sink 3A Up to 1MHz Switches Frequency Up to 94% Efficiency Internal PMOS/NMOS Switches - 70m/40m On-Resistance at VIN = 4.5V - 90m/60m On-Resistance at VIN = 3V
General Description
The APW7093 is a reversible energy flow, constantoff-time, pulse-width modulated (PWM), step-down DC-DC converter. It is ideal for use in notebook and sub-notebook computers that require 1.1V to 5V active termination power supplies. This device features an internal PMOS power switch and internal synchronous rectifier for high efficiency and reduced component count. The internal 90m PMOS power switch and 60m NMOS synchronous-rectifier switch easily deliver continuous load currents up to 3A. The APW7093 accurately tracks an external reference voltage, produces an adjustable output from 1.1V to VIN, and achieves efficiencies as high as 94%. The APW 7093 uses a unique current-mode, constant-off-time, PWM control scheme that allows the output to source or sink current. This feature allows energy to return to the input power supply that otherwise would be wasted. The programmable constant-off-time architecture sets switching frequencies up to 1MHz, allowing the user to optimize performance trade-offs between efficiency, output switching noise, component size, and cost. The APW7093 features an adjustable soft-start to limit surge currents during startup, a 100% duty-cycle mode for low-dropout operation, and a low-power shutdown mode that disables the power switches and reduces supply current below 1A. The APW7093 is available in a 32-pin QFN with an exposed backside pad or a 16-pin SSOP.
* * * * * * * * *
1% Output Accuracy 1.1V to VIN Adjustable Output Voltage 3V to +5.5V Input Voltage Range <1A Shutdown Supply Current Programmable Constant-Off-Time Operation Thermal Shutdown Adjustable Soft-Start Inrush Current Limiting Output Short-Circuit Protection Lead Free Available (RoHS Compliant)
Applications
* * * * * * *
Motherboard Graphics Cards Cable or DSL Modems, Set Top Boxes DSP Supplies Memory Supplies 5V Input DC-DC Regulators Distributed Power Supplies
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 1 www.anpec.com.tw
APW7093
Pin Description
SHDN N.C N.C N.C LX LX 32 1 N.C IN LX IN N.C SS N.C EXTREF 8 TOFF N.C N.C N.C GND REF N.C FB APW7093 PGND N.C VCC GND 17 N.C N.C 25 24 PGND PGND LX LX
SHDN IN LX IN SS EXTREF TOFF FB
1 2 3 4
16 15 14
LX PGND LX PGND VCC GND REF GND
13 APW7093 12 5 6 7 8 11 10 9
9
16
SSOP - 16
QFN - 32
Ordering and Marking Information
APW7093
Lead Free Code Handling Code Temp. Range Package Code
APW7093 N : APW7093 XXXXX
Package Code N : SSOP-16 QA : QFN -32 Operating Ambient Temp. Range I : -45 to 85 C Handling Code TU : TubeTR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device
XXXXX - Date Code
APW7093 QA :
APW7093 XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
2
www.anpec.com.tw
APW7093
Block Diagram
0.01 F VIN SS VCC FB IN CURRENT SENSE CIN VIN +3.0V TO +5.5V
+ EXTREF _ PWM LOGIC AND DRIVERS LX L
SHDN REF
COUT
REF
TIMER
GND
RTOFF
PGND
Fig1. Block Diagram
Absolute Maximum Ratings
Parameter VCC to GND IN to VCC GND to PGND Rating -0.3 ~ +6 0.3 0.3 -0.3 ~ VCC+0.3 -0.3 ~ VIN-1.7
2 2
Unit V V V V V W W A C C C C
SHDN , SS, FB, TOFF, VREF to GND
EXTREF to GND Power dissipation; Part mount on 1in of 1oz copper; QFN-28 Power dissipation; Part mount on 1in of 1oz copper; SSOP-16 LX Current Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature (soldering,10s)
1.6 1 -3.5 ~ +4.1 -40 ~ +85 +150 -65~+150 +300
Recommend Operating Condition
Recommend Operating Condition Symbol Parameter VIN Input Voltage Range VOUT Output Voltage Range COUT Output Capacitor CIN Input Capacitor L Inductor RTOFF
Programmed off-time Resistance
MIN 3 1.1 220 22 0.56
V
TYP
MAX 5.5 VIN
UNIT V V uF uF uH K
NOTE VEXTREF<= VIN-1.7V Low ESR Capacitor Refer to Application section for further Information.
www.anpec.com.tw
330 33 1
V V
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
3
APW7093
Electrical Characteristics
(VIN=VCC=3.3V, VEXTREF=+1.1V, TA=-45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC.)
Symbol Parameter Test Conditions APW7093 Min Typ Max 3.0 VIN=VCC=+3.0V to +5.5V, ILOAD=0,VEXTREF=1.25V (Note2) ILOAD=-3A to +3A, VEXTREF=+1.25V VREF 0.01 -12 20 VIN 1.7 5.5 +12 Unit V mV mV V V mV m m A MHz mA 15 A C 2.7 250 V nA s s s 5 6 A mA +1 0.8 SHDN Logic Levels 2.0 A V
VIN, VCC Input Voltage Feedback Voltage Accuracy (VFB -VEXTREF) VFB Feedback Load Regulation Error
VEXTREF External Reference Voltage Range VIN=VCC=+3.0 to +5.5V VREF Reference Voltage Reference Load Regulation RPMOS RNMOS ILIMIT fSW ICC IIN I SHDN PMOS Switch On-Resistance NMOS Switch On-Resistance Current Limit Threshold Switching Frequency No Load Supply Current Shutdown Supply Current Thermal Shutdown Threshold UVLO IFB Under Voltage Lockout Threshold FB Input Current IREF= -1A to +10A ILX=0.5A ILX=0.5A VIN > VLX (Note3) VIN=+4.5V VIN=+3.0V VIN=+4.5V VIN=+3.0V
1.07 1.10 1.12 8 0 2 0.3 70 90 50 60 3.5 4.1 2 140 180 100 120 4.7 1 1 32 <1 150 2.5 0 2.6 60
fSW =500kHz fSW =500kHz
SHDN = GND, ICC+ IIN Hysteresis =15C VCC falling, hysteresis = 90mV VFB=VEXTREF+0.1V RTOFF=30.1k
0.40 0.44 0.48 1.10 1.20 1.30 4.3 4.8 4xTOFF 5.3
TOFF
Off-Time
RTOFF=110k RTOFF=499k
Startup Off-Time TON ISS ISS On-Time SS Source Current SS Sink Current SHDN Input Current VIL VIH IOUT(RMS) Maximum Output RMS Current
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 4
(Note3)
0.34 4
VSS=1V VSHDN =0, VCC
2 -1
3.1 ARMS
www.anpec.com.tw
APW7093
Electrical Characteristics (Cont.)
(VIN=VCC=3.3V, VEXTREF=+1.1V, TA = -45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC.)
Symbol VIL VIH SHDN Logic Levels 2.0 IOUT(RMS) Maximum Output RMS Current Parameter Test Conditions APW7093 Min Typ Max 0.8 Unit V
3.1 ARMS
Note2: The output voltage will have a DC-regulation level lower than the feedback error comparator threshold by 50% of the ripple. Note3: Recommended operating frequency, not production tested.
Functional Pin Description
Name N.C IN PIN (QFN) 1,5,7,9,11,13,16,19, 25,26,28,30,32 2,4 PIN (QSOP) X 2,4 FUNCTION No Connection, Not internally connected. Supply Voltage Input for the internal PMOS Power Switch. Not internally connected. Externally connect all pins for proper operation. Inductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifier switch. Connect the inductor from this node to the output filter capacitor and load. Not internally connected. Externally connect all pins for proper operation. Soft-Start Connect a capacitor from SS to GND to limit inrush current during startup. External Reference Input Feedback input regulates to VEXTREF. The PWM controller remains off until EXTREF is greater than REF. Off-Time Select Input. Sets the PMOS power switch constant-off-time. Connect a resistor from TOFF to GND to adjust the PMOS switch off-time. Feedback Input. Connect directly to output for fixed-voltage operation or to a resistive-divider for adjustable operating modes. Analog Ground. Connect exposed backside pad and corner tabs to analog GND. Reference Output. Bypass REF to GND with a 0.1F capacitor. Tie to GND (pin 13 QFN; pin 9 SSOP) Analog Supply Voltage Input. Supplies internal analog circuitry. Bypass VCC with a 10 and 1F low-pass filter. See Figure2. Power Ground. Internally connected to the internal NMOS synchronous-rectifier switch. Shutdown control Input Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs. Drive high or connect to VCC for normal operation.
5 www.anpec.com.tw
LX
3,21,22,27,29
3,14,16
SS EXTREF
6 8
5 6
TOFF
10
7
FB GND REF GND VCC PGND SHDN
12 14,17,backside pad, corner tabs 15 17 18 20,23,24 31
8 9 10 11 12 13,15 1
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
APW7093
Typical Application
APW7093 VIN IN 10 33F PGND VCC 1F SHDN VEXTREF EXTREF TOFF RTOFF FB REF SS 0.1F 0.01F 50K GND R2 LX 220F 15m L VOUT
FOR VIN =5V: L=1mH, RTOFF=100kW FOR VIN=3.3V: L=0.68mH, RTOFF=68kW Fig2. Typical Applicatin Circuit
Typical Characteristics
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68H, RTOFF=68k; for VIN=5V: L=1H, TOFF=100k. TA=25C if not specially)
Effienciency vs. Output Current
100 95 90 85
No Load Supply Current vs. Input Voltage
50
VIN=5V, VOUT=3.3V
No Load Supply Current(mA)
40
Efficiency(%)
80 75 70 65 60 55 50 45 40 0 1 2 3
30
VIN=5V, VOUT=1.25V VIN=5V, VOUT=2.5V VIN=3.3V, VOUT=1.25V
VOUT=1.25V RTOFF=68k
20
10
0 0 1 2 3 4 5 6
Output Current(A)
Input Voltage(V)
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
6
www.anpec.com.tw
APW7093
Typical Characteristics (Cont.)
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68H, RTOFF=68k; for VIN=5V: L=1H, TOFF=100k. TA=25C if not specially)
Switching Frequency vs. Output Current
900
6
OFF-TIME vs. RTOFF
Switching Frequency(kHz)
800 700
5
VIN=3.3V
600 500 400 300 200 100 0 0 1 2 3
1
OFF-TIME(s)
4
3
VIN=5V
2
0 0 100 200 300 400 500 600
Output Current(A)
RTOFF(k)
VREF vs. Input Voltage
1.114
Start Up and Shut Down
SHDN=2V/DIV
1.113
VREF(V)
1.112
VSS=2V/DIV
1.111
IN=1A/DIV
1.110 3.0
3.5
4.0
4.5
5.0
5.5
TIME 2ms/DIV
Input Voltage(V)
VIN=3.3V, VOUT=1.25V, ROUT=0.4
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
7
www.anpec.com.tw
APW7093
Typical Characteristics (Cont.)
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L= 0.68H, RTOFF=68k; for VIN=5V: L=1H, TOFF=100k. TA=25C if not specially)
Load Transient Response
IOUT=3A
Load Transient Response
IOUT=3A
IOUT= 3A
IOUT=0A
IOUT=0A 0A IOUT=
VOUT 100mV/DIV
VOUT 100mV/DIV
VOUT 100mV/DIV
TIME 20s/DIV TIME 20us/DIV
TIME 20s/DIV
di
VIN=5V, VOUT=1.25V,
dt
=
3A s
di
VIN=5V, VOUT=2.5V,
dt
=
3A s
Load Transient Response
Line Transient Response
IOUT=3A VIN=5.0V IOUT=0A VIN=3.0V
VOUT 100mV/DIV
VOUT 100mV/DIV
TIME 20s/DIV
TIME 40s/DIV
VIN=3.3V, VOUT=1.25V, di
dt
=
3A s
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
8
www.anpec.com.tw
APW7093
Typical Characteristics (Cont.)
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L= 0.68H, RTOFF=68k; for VIN=5V: L=1H, TOFF=100k. TA=25C if not specially)
Light Load Waveform
VLX 5V/DIV
Heavy Load Waveform
VLX 5V/DIV
ILX 1A/DIV
ILX 1A/DIV
VOUT 50mV/DIV
VOUT 50mV/DIV
TIME 1s/DIV
TIME 1s/DIV
IOUT=100mA
IOUT=3A
VREF vs. Temperature
1.118 1.116 1.114 1.112
Output Voltage vs. Temperature
1.255
1.253
VIN=3.3V
VREF(V)
VOUT(V)
1.110 1.108 1.106 1.104 1.102 1.100 1.098 -50 -25 0 25 50 75 100 125
1.251
VIN=3.3V IOUT=0A
1.249
1.247
1.245 -50 -25 0 25 50 75 100 125
Temperature(C)
Temperature(C)
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
9
www.anpec.com.tw
APW7093
Function Descriptions
The APW7093 synchronous, current-mode, constant off-time, PW M DC-DC converter steps down input voltages of 3V to 5.5V to an adjustable output voltage from 1.1V to VIN, as set by the voltage applied at EXTREF. It sources and sinks up to 3A of output current. Internal switches composed of a 90m[ PMOS power switch and a 60m [ NMOS synchronous-rectifier switch improve efficiency, reduce component count, and eliminate the need for an external Schottky diode across the synchronous switch. The APW7093 operates in a constant-off-time mode under all loads. A single resistor-programmable constant- tradeoffs in efficiency, switching noise, component size, and cost. When power is drawn from a regulated supply, constant-off-time PWM architecture essentially provides constant-frequency operation. This architecture has the inherent advantage of quick response to line and load transients. The APW7093' s current-mode, constant-off-time PWM architecture regulates the output voltage by changing the PMOS switch on-time relative to the constant off-time. path for current to flow when the inductor is discharging. Replacing the Schottky diode with a low-resistance NMOS synchronous switch reduces conduction losses and improves efficiency. The NMOS synchronous-rectifier switch turns on following a short delay (typ. 20ns) after the PMOS power switch turns off, thus preventing cross-conduction or "shoot-through." In constant-offtime mode, the synchronous-rectifier switch turns off just prior to the PMOS power switch turning on. While both switches are off, inductor current flows through the internal body diode of the NMOS switch.
Constant-Off-Time Operation
In the constant-off-time architecture, the FB voltage comparator turns the PMOS switch on at the end of each off-time, keeping the device in continuousconduction mode. The PMOS switch remains on until the feedback voltage exceeds the external reference voltage (VEXTREF) or the positive current limit is reached. When the PMOS switch turns off, it remains off for the programmed off-time (TOFF). To control the current under short-circuit conditions, the PMOS switch remains off for approximately 4 x TOFF when VFB < VEXTREF / 4.
Current Sourcing and Sinking By operating in a constant-off-time, pseudo-fixedfrequency mode, the APW7093 can both source and sink current. Depending on the output current requirement, the circuit operates in two modes. In the first mode the output draws current and the APW7093 behaves as a regular buck controller, sourcing current to the output from the input supply rail. However, when the output is supplied by another source, the APW7093 operates in a second mode as a synchronous boost, taking power from the output and returning it to the input. Thermal Resistance
Junction-to-ambient thermal resistance, c JA, is highly dependent on the amount of copper area immediately surrounding the IC leads. The APW7093 QFN package has 1in square of copper area and a thermal resistance of 50C/W with no forced airflow. The APW 7093 16-pin SSOP evaluation kit has 0.5 in square of copper area and a thermal resistance of 80C/ W with no forced airflow. Airflow over the board significantly reduces the junction-to-ambient thermal resistance. For heat sinking purposes, it is essential to connect the exposed backside pad of the QFN package to a large analog ground plane.
Synchronous Rectification
In a step-down regulator without synchronous rectification, an external Schottky diode provides a
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 10
www.anpec.com.tw
APW7093
Function Descriptions(Cont.)
Shutdown
Drive SHDN to a logic-level low to place the APW7093 in low-power shutdown mode and reduce supply current less than 1A. In shutdown, all circuitry and internal MOSFETs turn off, so the LX node becomes high impedance. Drive SHDN to a logic-level high or connect to VCC for normal operation.
PD(CAP) = C x VIN x fSW
where C = 500pF and fSW is the switching frequency. Resistive losses in the two power switches are approximated by:
2
PD(RES) = IOUT x R PMOS
where RPMOS is the on-resistance of the PMOS switch. The junction-to-ambient thermal resistance required to dissipate this amount of power is calculated by: cJA = (TJ,MAX - TA,MAX) / (PD(CAP) + PD(RES)) where: c JA = junction-to-ambient thermal resistance TJ,MAX = maximum junction temperature TA,MAX = maximum ambient temperature
2
Power Dissipation
Power dissipation in the APW7093 is dominated by conduction losses in the two internal power switches. Power dissipation due to charging and discharging the gate capacitance of the internal switches (i.e., switching losses) is approximately:
Application Information
For typical applications, use the recommended component values in Figure 2. For other applications, take the following steps: 1. Select the desired PWM-mode switching frequency. See Figure 3 for maximum operating frequency. 2. Select the constant off-time as a function of input voltage, output voltage, and switching frequency. 3. Select RTOFF as a function of off-time. 4. Select the inductor as a function of output voltage, off-time, and peak-to-peak inductor current.
1400
Setting the Output Voltage
An external voltage applied to the EXTREF pin sets the output voltage of the APW7093. This can come directly from another voltage source or external reference. When FB is directly tied to the output (Figure 4), the output voltage range is limited by the external reference' input voltage limits. VEXTREF s should be limited to less than VIN-1.7V. Failure to comply can cause the part to operate abnormally and may cause part damage. Alternatively, the output can be adjusted up to VIN by connecting FB to a resistordivider between the output voltage and ground (Figure 5). Use 50k [ for R1. R2 is given by:
R2 = R1 VOUT - 1 VEXTREF
Operation Frequency(KHz)
VOUT=2.5V
1200 1000 800 600 400 200 0 2.8 3.3 3.8 4.3 4.8 5.3
VOUT=1.1V VOUT=1.25V VOUT=3.3V
Input Voltage(V) Fig 3. Maximum Recommended Operation Frequency
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 11 www.anpec.com.tw
APW7093
Application Information(Cont.)
Setting the Output Voltage (Cont.)
TOFF =
VOUT=VEXTREF where: LX APW7093
(VIN - VOUT - VPMOS ) fSW (VIN - VPMOS + VNMOS )
TOFF = the programmed off-time VIN = the input voltage VOUT = the output voltage VPMOS = the voltage drop across the internal PMOS power switch |IOUT X RPMOS| VNMOS = the voltage drop across the internal NMOS synchronous-rectifier switch |IOUT X RNMOS| fSW = switching frequency Make sure that TON and TOFF are greater than 400ns when sourcing current. Select RTOFF according to the formula:
VEXTREF EXTREF FB
1.1V VEXTREF VIN - 1.7V
FIG.4 Adjsting the Output Voltage using EXTREF
VOUT LX APW7093 FB EXTREF REF R1
R TOFF = (TOFF - 0.18 s) x (109k /1.00 s )
Recommended values for RTOFF range from 24k [ to
R2
410k [ for off-times of 0.4s to 4s. Often the switching frequency is set as high as possible, and the inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step recovery. The operating frequency of the APW7093 is determined primarily by TOFF (set by RTOFF), VIN, and VOUT as shown in the following formula:
R 2 = R1
- 1 VEXTREF
V OUT
fSW =
(VIN - VOUT - VPMOS ) TOFF (VIN - VPMOS + VNMOS )
where VEXTREF = VREF = 1.1V FIG.5 Adjsting the Output Voltage using FB
Programming the Switching Frequency and Off-Time and On-Time
The APW7093 features a programmable PWM-mode switching frequency, which is set by the input and output voltage and the value of RTOFF, connected from TOFF to GND. RTOFF sets the PMOS power switch off-time in PWM mode. Use the following equation to select the off-time while sourcing current according to the desired switching frequency in PWM mode:
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 12
However, as the output current increases, the voltage drop across the NMOS and PMOS switches increases and the voltage across the inductor decreases. This causes the frequency to drop. Assuming RPMOS = RNMOS, the change in frequency can be approximated with the following formula:
fSW =
- IOUT x RPMOS
VIN x TOFF
where RPMOS is the resistance of the internal MOSFETs (70m [ typ).
www.anpec.com.tw
APW7093
Application Information(Cont.)
Programming the Switching Frequency and Off-Time and On-Time (Cont.)
W hen sinking current, the switching frequency increases due to the on-resistances of the internal switches adding to the voltage across the inductor, reducing the on-time. Calculate TON when sinking current using the equation:
Low-ESR and low-ESL Tantalum or ceramic capacitor should be suitable.
Output Capacitor Selection
The output filter capacitor affects the output voltage ripple, output load-transient response, and feedback loop stability. The output filter capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to guarantee stability and absorb the inductor energy going from a full-load sourcing to full load sinking condition without exceeding the maximum output tolerance. In applications where the output is subject to large load transients, the output capacitor' size typically s depends on how much ESR is needed to prevent the output from dipping too low under a load transient.
TON = TOFF
VOUT - VNMOS
VIN - VOUT + VPMOS

Inductor Selection
The key inductor parameters must be specified: inductor value (L) and peak current (IPEAK). A lower value of inductor allows smaller size but results in higher losses and ripple. A good compromise between size and losses is found at approximately a 25% ripple current to load current ratio (I/IOUT = 0.25).
L=
VOUT x TOFF IOUT x 0.25
R ESR VOUT / I OUT(MAX)
The actual microfarad capacitance value required is defined by the physical size needed to achieve low ESR, and by the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR, size and voltage rating rather than by capacitance value. W hen using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent overshoot and undershoot from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising-load edge is no longer a problem.
The peak inductor current at full load is calculated by:
IPEAK = IOUT +
VOUT x TOFF 2xL
where IOUT is the maximum source or sink current. Choose an inductor with a saturation current at least as high as the peak inductor current. Additionally, verify the peak inductor current while sourcing output current (IOUT = ISOURCE) does not exceed the positive current limit. The inductor selected should exhibit low losses at the chosen operating frequency.
Input Capacitor Selection
The input filter capacitor reduces peak currents and noise at the voltage source. A 22F to 47F capacitor
may be required for higher power and dynamic loads.
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005 13 www.anpec.com.tw
APW7093
Application Information(Cont.)
Soft-Start
Soft-start allows a gradual increase of the internal current limit to reduce input surge currents at startup and at exit from shutdown. A timing capacitor, CSS, placed from SS to GND sets the rate at which the internal current limit is changed. Upon power-up, when the device comes out of under-voltage lockout (2.6V typ.) or after the SHDN pin is pulled high, a 4.7A constant current source charges the soft-start capacitor and the voltage on SS increases. When the voltage on SS is less than approximately 0.7V, the current limit is set to zero. As the voltage increases from 0.7V to approximately VIN, the current limit is adjusted from 0V to the current-limit threshold. The voltage across the soft-start capacitor changes with time according to the equation:
Input Source
The output of the APW7093 can accept current due to the reversible properties of the buck and the boost converter. When voltage at the output of the APW7093 (low-voltage port) exceeds or equals the output set voltage the flow of energy reverses, going from the output to the input (high-voltage port). If the input (high voltage port) is not connected to a low-impedance source capable of absorbing energy, the voltage at the input will rise. This voltage can violate the absolute maximum voltage at the input of the APW7093 and destroy the part. This occurs when sinking current because the topology acts as a boost converter, pumping energy from the low-voltage side (the output), to the high-voltage side (the input). The input (highvoltage side) voltage is limited only by the clamping effect of the voltage source connected there. To avoid this problem, make sure the input to the APW7093 is connected to a low impedance, two quadrant supply or that the load (excluding the APW7093) connected to that supply consumes more power than the amount being transferred from the APW7093 output to the input.
VSS =
4.7 A x t C SS
The output current limit during soft-start varies with the voltage on the soft-start pin, SS, according to the equation:
ILIIM(SS)=
(V - 0.7V) SS xILIMIT , VSS 1.8V 1.1V
Current Limit and Short Circuit Protection
The APW7093 monitors sourcing and sinking current, and limits the maximum output current to prevent damages during overload or short-circuit.
where ILIMIT is the current-limit threshold from the Electrical Characteristics. The constant-current source stops charging once the voltage across the soft-start capacitor reaches 1.8V.
SHDN
Circuit Layout and Grounding
Good layout is necessary to achieve the APW7093' s intended output power level, high efficiency, and low noise. Good layout includes the use of ground planes, careful component placement, and correct routing of traces using appropriate trace widths. The following points are in order of decreasing importance:
0
VIN V SS(A) 0.7V 1.8V
0
ILIMIT(A) ILIMIT
0 Fig6. Soft-Start Current Limit
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
t
14
www.anpec.com.tw
APW7093
Application Information(Cont.)
Circuit Layout and Grounding (Cont.)
1. Minimize switched-current and high-current ground loops. Connect the input capacitor' ground, the s output capacitor' ground, and P GND close s together. Split the ground connections. Use separate traces or planes for the PGND and GND and tie them together at a single point. 2. The output capacitor should be placed close to the output terminals to obtain better smoothing effect on the output ripple. 3. Connect the input filter capacitor less than 5mm away from IN. The connecting copper trace carries large currents and must be at least 1mm wide, preferably 2.5mm. 4.Place the LX node components as close together and as near to the device as possible. This reduces resistive and switching losses as well as noise. 5.G round planes are e ssent ial f o r opti m um performance. In most applications, the circuit is located on a multilayer board and full use of the four or m ore layers is recom m ended. For heat dissipation, connect the exposed backside pad of the QFN package to a large analog ground plane, preferably on a surface of the board that receives good airflow. If the ground plane is located on the top layer, make use of the N.C. pins adjacent to GND to lower thermal resistance to the ground plane. If the ground is located elsewhere, use several vias to lower thermal resistance. Typical applications use multiple ground planes to m inim ize therm al resistance. Avoid large AC currents through the analog ground plane.
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
15
www.anpec.com.tw
APW7093
Packaging Information
SSOP-16
S D N
H
E
GAUGE PLANE
1
2
3
A e B A1
L
1
Millimeters Dim A A1 B D E e H L S 1 5.75 0.4 0.05 0 Min. 1.350 0.10 0.20 4.75 3.75 0.625 TYP. 6.25 1.27 0.18 8 0.226 0.016 0.002 0 Max. 1.75 0.25 0.30 5.05 4.05 Min. 0.053 0.004 0.008 0.187 0.147
Inches Max. 0.069 0.010 0.012 0.199 0.160 0.025 TYP. 0.246 0.050 0.007 8
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
16
www.anpec.com.tw
APW7093
Packaging Information
QFN-32
D
32 1 2 3 22 4 21 5 31 30 29 28 27 26 25 24 23
D2
31 32 1 2
L
E
E2
20 19
6
7 8 9 10 11 12 13 14 15 16
18 17
e
b
A A3 A1
Dim A A1 A3 D E b D2 E2 e L
Millimeters Min. 0.00 0.20 REF. 4.90 4.90 0.18 3.50 3.50 0.500 BSC 0.35 0.45 0.014 5.10 5.10 0.28 3.60 3.60 0.192 0.192 0.007 0.138 0.138 Max. 0.84 0.04 Min. 0.00
Inches Max. 0.033 0.0015 0.008 REF. 0.200 0.200 0.011 0.142 0.142 0.020 BSC 0.018
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
17
www.anpec.com.tw
APW7093
Physical Specifications
Terminal Material Lead Solderability Packaging Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. 2500 devices per reel
(IR/Convection or VPR Reflow)
Reflow Condition
TP
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (T L) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright (c) ANPEC Electronics Corp. 18 www.anpec.com.tw
Rev. A.5 - Jun., 2005
APW7093
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperature s Package Thickness Volume mm 3 Volume mm 3 <350 350 <2.5 mm 240 +0/-5C 225 +0/-5C 2.5 mm 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability test program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C , 5 SEC 1000 Hrs Bias @ 125 C 168 Hrs, 100 % RH , 121C -65C ~ 150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 100mA
Carrier Tape & Reel Dimension
t E Po P P1 D
F W
Bo
Ao
D1
Ko
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
19
www.anpec.com.tw
APW7093
Carrier Tape & Reel Dimension
T2
J C A B
T1
Application
A 6.95
B 5.4 T2 2.2
D0
D1
E 1.750.1 C1 130.3
F 5.50.05 C2 210.8
P0 4.00.1 T1 13.50.5
P1 8.00.1 T2 2.00.2
P2 2.00.05 C 801
1.550.05 1.550.1 W 12.00.3 W1 9.5
SSOP-16
T 0.30.05
(mm)
Cover Tape Dimensions
Application SSOP- 16 Carrier Width 16.8 Cover Tape Width 12.3 Devices Per Reel 2500
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Jun., 2005
20
www.anpec.com.tw

▲Up To Search▲

Price & Availability of APW7093NI-TRL

	To Download APW7093NI-TRL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .